Introduction

In previous sections, we learned about algorithmic approaches to speed up bioinformatic analysis. Such algorithmic approaches tend to target the widest class of devices and therefore tend to make assumptions about the most generic hardware. In many situations, paying an upfront fee for better hardware can lead to substantial improvement in performance. One good example is de Bruijn graph-based genome assembly, where a high-RAM machine has become essential in being able to run several high-performance algorithms.

In section 1, we presented the architecture of modern computers. Each component in the presented system - hard disk, RAM, processor and even their connecting system (‘bus architecture’) - can be upgraded to boost performance. This section covers the impact of such changes in hardware on algorithm design and performance.

Understanding hardware infrastructure requires different analytical mindset than designing software programs. Algorithms are abstractions of underlying computing system and are usually presented in mathematical language. In contrast, hardware is described in physical terms, and factors such as physical location, type of connections, speed, latency, etc. come into consideration to model performance gain through hardware replacement.

Second important difference between hardware and software solutions is in the way an user pays for the improvements. Software programs can be continually changed or rewritten, and an error made in an earlier design can be easily fixed in future. Hardware upgrades, on the other hand, are fully paid right at the time of installation and enjoyed over the lifetime of the component. That requires far more careful planning, because selecting the wrong architecture can significantly reduce options available to programmers. Those cautions do not mean creative hardware-based solutions should be avoided altogether, because hardware, being infinitely parallelizable, can dramatically boost performance, when speed of analysis is the primary concern.

In the hardware world, the best way to visualize a complex data-intensive computing is by thinking about how data flows through logical and storage components of the machine. Just like water flows through pipes and channels avoiding barriers, during the course of a computation, data flows from its original location through millions of intelligent pipes and channels and gets morphed into the output by logical units. A carefully crafted solution removes barriers and creates as many parallel channels as possible so that data can flow very rapidly through the computing ‘pipes and channels’. For a simple example, let us say your computer has one chip that can only add numbers. However, you can write code to use the adder many times to multiply numbers. That is a software solution. On the other hand, you can build a new multiplication chip. (Incidentally, designing efficient multiplication algorithms for VLSI chips was seemed like the most difficult problem in our undergraduate class of digital circuits 101, until we got involved into making the whole enchilada – an entire microprocessor – in the next class). The above example shows the relative merits and demerits of two approaches. Software approach is easy to implement, but runs slow. Hardware approach can be very fast, but is difficult and expensive to build. The biggest expense of using custom chips comes from creating hardware masks for photo-lithography of the transistor gates and their interconnections, because what the software approach did through coding is essentially replicated by connecting transistor gates in the hardware approach.